The present invention relates to a semiconductor integrated circuit including a control block, for example, a processor, of a stored-program type.
Japanese Laid-Open Publication No. 6-131218 discloses a technique which utilizes a watch dog timer (WDT) as one of the processor (CPU) control techniques in which an abnormal condition in a computer system is detected to reset the CPU. The WDT, which monitors a counter reset signal outputted regularly from the CPU, outputs a time-over signal if the counter reset signal has not been inputted within a given period of time because of a program runaway. The time-over signal outputted from the WDT resets the CPU for recovery to the normal state.
However, a problem with the conventional technique has been that because the CPU is reset to the initial state by the time-over signal, the program is re-executed from the beginning, as a result of which the data is destroyed midway.